1. Field of the Invention
This disclosure relates to a method of fabricating a semiconductor device, and particularly to, a method of fabricating a transistor with a recessed channel.
2. Description of the Related Art
As integrated circuit semiconductor devices become more integrated and design rules decrease dramatically, it becomes increasingly difficult to stably operate a transistor. For instance, a reduction in the design rule reduces a gate width, thus reducing a short length of the transistor. As a result, short channel effects frequently occur.
The short channel effect causes a punch through between source and drain regions of the transistor. Punch-through is considered a major factor that causes malfunctioning of the transistor. To solve problems caused by the short channel effect, much research on methods of increasing a channel length regardless of a reduction in the design rule has been conducted. For instance, an MOS transistor with a recessed channel, which is obtained by recessing portions of a semiconductor substrate below gates, is designed to increase a channel length with respect to a limited gate dimension.
FIGS. 1A and 1B are schematic cross-sectional views for explaining problems with fabricating a conventional transistor with a recessed channel. Referring to FIG. 1A, a recessed channel is obtained by forming a first trench 2 in a semiconductor substrate 1 and forming a gate 3 to fill the first trench 2. The recessed channel is formed along the profile of the first trench 2, that is, at the bottom and sidewalls thereof. Thus, the length of the recessed channel is longer than a critical dimension of the gate 3.
However, as illustrated in FIG. 1B, during manufacture of the transistor with such a recessed channel, a residual material 7, e.g., silicon (Si), from the semiconductor substrate 1 may remain between an isolation layer 5 and the gate 3 filling the first trench 2. The isolation layer 5 is obtained in an isolation process preceding the manufacture of the transistor.
When the material 7, e.g., a silicon residual substance, is interposed between the gate 3 and the isolation layer 5, a leakage current is prone to occur where the silicon residual substance 7 is formed. Further, the silicon residual substance 7 may cause short circuiting between source/drain regions or a change in a threshold voltage Vth.
The occurrence of the silicon residual substance 7 is caused by an inclination of the sidewalls of a second trench 6 with respect to the isolation layer 5. That is, the sidewall profile of the second trench 6 is not perpendicular to and is inclined at an angle with respect to the isolation layer 5. Thus, a width d1 of an upper portion of an active area defined by the isolation layer 5 is narrower than a width d2 between bottom corners of the second trench 6.
The inclination of the sidewall profile of the second trench 6 with respect to the isolation layer 5 inevitably causes the generation of the silicon residual substance 7 between sidewalls of the first trench 2 and the second trench 6, i.e., at an interface between the gate 3 and the isolation layer 5. Also, it is almost impossible to realize the first and second trenches 2 and 6 with perpendicular sidewall profiles using an etching process of forming the first and second trenches 2 and 6. Further, a very tight process margin is needed to fabricate the second trench 6 to include perpendicular sidewalls, and it is difficult to make the isolation layer 5 completely fill the second trench 6.
Accordingly, an additional process of removing the silicon residual substance 7 is required. For instance, the silicon residual substance 7 must be removed using anisotropic etching, e.g. chemical dry etching, on the first trench 2.
However, the additional process leads to an increase in a critical dimension (CD) of the first trench 2 below the gate 3, thus causing nonuniformity in the length of the recessed channel. The increase in the CD of the first trench 2 also deteriorates topology of a polycrystalline silicon layer which is deposited to fill the first trench 2 and form the gate 3. In this case, when forming a conductive layer, such as a tungsten silicide (WSix) layer, on the polycrystalline silicon layer, the tungsten silicide (WSix) layer may break into pieces.
Accordingly, there is a strong need to develop a method of fabricating a transistor with a recessed channel where a material such as the silicon residual substance 7 of FIG. 1B does not remain between the sidewalls of the first trench 2, the recessed channel, and the isolation layer 5.
Embodiments of the invention address these and other disadvantages of the conventional art.